General Information
Paper Suggestions
- Pangaea: A Tightly-Coupled IA32 Heterogeneous Chip Multiprocessor - PACT'08
- Exochi: Architecture and Programming Environment for a Heterogenous Multi-core Multithreaded System - PLDI'07
- Wisconsin paper on ray-tracing hardware - MICRO'08
- Strategies for Mapping Dataflow Blocks to Distributed Hardware - MICRO'08
- Composable Lightweight Processors - MICRO'07
- Feedback driven threading: Power-efficient and High-performance execution of multithreaded workloads on CMPs - ASPLOS'08
- Rerun: Exploiting Episodes for Lightweight Memory Race Recording - ISCA'08
- A Small Cache of Large Ranges: Hardware Methods for Efficiently. Searching, Storing, and Updating Big Dataflow Tags. - MICRO'08
- Corona: System Implications of Emerging Nanophotonic Technology - ISCA'08
Class Schedule
| Date | Presenter | Paper/Link |
|---|
| 3rd Sep | Manu | Scavenger: A New Last Level Cache Architecture with Global Block Priority,MICRO 2007 |
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| 10th Sep | No Meeting | PhD Defenses This Week |
| 17th Sep | Kshitij | Cache Bursts: A New Approach for Eliminating Dead Blocks and Increasing Cache Efficiency, MICRO 2008 |
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| 24th Sep | David | Operating System Power Minimization through Run-time Processor Resource Adaptation, Microprocessors and Microsystems, June 2006 |
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| 1st Oct | Aniruddha | Polymorphic On-Chip Networks, ISCA 08 |
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| 8th Oct | Tim Hollis of Micron Technology, Inc | MICRON TECHNICAL SEMINAR: Challenges and Opportunities in Memory System Design |
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| 15th Oct | | Fall Break |
| 22nd Oct | Byong Wu | The Adaptive Transactional Memory Test Platform: A Tool for Experimenting with Transactional Code for Rock ( slides ), Applications of the Adaptive Transactional Memory Test Platform ( slides ), Transact, February 23, 2008 |
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| 29th Oct | Niladrish | Designing An Efficient Kernel-level and User-level Hybrid Approach for MPI Intra-node Communication on Multi-core Systems, Int'l Conference on Parallel Processing (ICPP) 2008 |
|---|
| 5th Nov | Manu | Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, MICRO 2007 Follow-up papers - Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, 3D-Stacked Memory Architectures for Multi-Core Processors, ISCA '08 |
|---|
| 12th Nov | No meeting | |
| 19th Nov | Dan proposal | |
| 26th Nov | | |
| 3rd Dec | Devyani | Self-optimizing memory controllers: A Reinforcement Learning Approach, ISCA '08, Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach MICRO '08 |
|---|
| 10th Dec | | |
Recent Conference Programs
